VHDL Information

  »  Using VHDL attributes to automatically check the timing of your design in the testbench.

  »  Initialising signals for simulation.

  »  Use generate statements to create Relationally Placed Macros.

  »  Create basic input stimuli for simulation.

  »  Text files for simulation input/output : Recording & reporting messages from the testbench.

  »  Generating random values in a VHDL testbench.

  »  Saving the ModelSim Wave Window Format for ISE9.2.

  »  Saving the ModelSim Wave Window Format for ISE10.1.

  »  Adding a hardware timestamp to your FPGA.