PROBE is a debugging feature available in the Xilinx™ toolset that allows
the user to quicjly and easily connect internal signals to unused pins without
modifying the source code, resynthesizing or recompiling the design.
The original design is not altered in any way, the only thing that is added is extra routing from the internal nodes to the unused pins. This means that the timing will remain the same.
After place and route (PAR) is completed, an .ncd file is generated which can be opened and modified with FPGA Editor.
1. After compilation is finished, open the routed .ncd file with
Figure 1: Open FPGA Editor
2. Change into Read Write Mode as follows: File -> Main Properties.. then select Read Write as the Edit mode.
Figure 2: Set Read Write mode.
3. Open the Probes window by selecting the probes button at the right side of the FPGA Editor window.
Figure 3: Open Probes Window.
4. Open the Define Probe window by clicking on the Add button at the top right corner of the Probes window.
Figure 4: Open Define Probe Window.
5. Give a name to the new pin that will be added. Then select the
net that will be wired to the unused pin.
The pin location can either be selected manually or automatically by FPGA Editor.
Figure 5: Select the net and pin.
6. Generate the new bitstream.
Figure 6: Generate new bitstream.
7. Download the bitstream and start debugging!