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FPGA Design

[ Timing Constraints | Design Tips | Debug Tips | Power Reduction ]

This page contains links to FPGA design information.

Timing Constraints

  » Basic Timing Constraints.
  » Advanced Methods For Specifying Clock Frequencies.
  » Timing Constraints for DDR inputs.

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Design Tips

  » Using LFSRs.
  » INIT attribute for LUTs.
  » Preserve Routing With Constraints.
  » FPGA Reset Strategies.
  » Clock division with SRL primitives.

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Debug Tips

» Debugging with PROBE.

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Power Reduction

» Part 1 - Reducing Static Power.
» Part 2 - BlockRAM and DSP48s.

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